1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a circuit operating on the basis of a clock signal.
2. Description of the Prior Art
In relation to an ASIC (application specific integrated circuit) readily implementing a device for a specific application with CAD (computer aided design), a gate array system, a standard cell system and an embedded array system are well known in general as methods of efficiently designing a semi-custom LSI.
In the gate array system, basic cells covered with transistors in the form of arrays are arranged and wired for forming a logic circuit, and the design TAT (turn-around time) is advantageously reduced.
In the standard cell system, optimally designed verified macro cell parts are previously registered in a design database for CAD so that the macro cell parts are arbitrarily combined by CAD. According to this method, large-sized macro cell parts such as a CPU (central processing unit) and a memory are easy to design although the design TAT is longer than that in the gate array system.
In the embedded array system, employing the advantages of both of the gate array system and the standard cell system, macro cell parts of standard cells are embedded in a random logic part of a gate array.
When designing an ASIC, power supply wires are necessary for fixing signal lines in the circuit to a power supply potential or a ground potential. According to Japanese Patent Laying-Open No. 8-125025 (1996), for example, power supply potential wires and ground potential wires are provided in the form of rings for enclosing a microcomputer core as macro cell parts in a design of an ASIC microcomputer.
In a synchronous design for operating a plurality of logic circuits in synchronization with a clock signal, a large current instantaneously flows to power supply wires since the clock signal-makes transition an extremely large number of times as compared with other signals and the logic circuits are designed to simultaneously operate due to the synchronous design. Thus, the power supply wires readily cause voltage drops. When the power supply wires cause voltage drops, data signals processed in the logic circuits cause noise, waveform rounding or delay degradation, leading to malfunctions.